This invention relates to a coincidence determination circuit, and more particularly to a coincidence determination circuit for coincidence determination of multiple data of multi-bits, comprised of combined CMOS type FETs.
The coincidence determination of two data signals can be normally realized by using an exclusive logical sum circuit (which will be referred to as "EOR" hereinafter). Accordingly, the coincidence determination circuit for determining coincidence between two multi-bit data can be realized by combining a puurality of EORs.
In a conventional coincidence determination circuit, the number of semiconductor elements is considerably increased in accordance with the increase in the number of bits of data to be compared, resulting in the problem that the occupation area of elements increases when an attempt is made to realize such a circuit with a semiconductor integrated circuit.
Moreover, in the conventional coincidence determination circuit, the number of wirings coupling EORs for comparing each bit and a NOR circuit for determining the coincidence among all bits becomes large, resulting in the problem that the occupation area of elements also becomes large.